The current work introduces a method for predicting Memcached throughput on single-core and multi-core processors.
The method is based on traces collected from a full system simulator running Memcached.
A series of microarchtectural simulators consume these traces and the results are used to produce a CPI model
composed of a baseline issue rate, cache miss rates, and branch mispredictions rate.
Simple queueing models are used to produce througput predictions with accuracy in the range of 8% to 17%.